Recently, as the integration degree of semiconductor devices increases, the degree of micropatterning of circuit patterns of, e.g., transistors of these devices increases. Since this micropatterning makes interconnections thinner, techniques for increasing the dimensional accuracy and positional accuracy of circuit patterns are necessary. This situation is not an exception in the field of semiconductor memories as well.
Conventionally known commercially available semiconductor memories such as a DRAM, SRAM, and flash memory use a MOSFET as a memory cell. A semiconductor memory like this requires an increase in dimensional accuracy at a ratio higher than that of micropatterning of circuit patterns. This imposes a large load on the photolithography technique of forming fine circuit patterns, and this is one cause of raising the product cost.
A resistance change memory is attracting attention as a memory successor candidate that solves this problem.
The resistance change memory stores data by using a change in resistance value of a resistance change element. Since the resistance change memory is a two-terminal element, it is possible to reduce the cost by using a simplified process, and increase the capacity by using a three-dimensional (cross-point type) resistance change memory. Accordingly, the resistance change memory is expected as a next-generation nonvolatile semiconductor memory.
An operation of changing the resistance value of the resistance change element from a high-resistance state to a low-resistance state in the resistance change memory is performed by applying a voltage pulse to the resistance change element. Also, the resistance value in the low-resistance state after this operation is complete depends on a maximum electric current having flown through the resistance change element during the operation. That is, the resistance value in the low-resistance state varies in accordance with the variation in maximum electric current flowing through the resistance change element during the operation.
To prevent this, a technique that adds a current limiting function of limiting the maximum electric current flowing through the resistance change element to the operation of changing the resistance value of the resistance change element from the high-resistance state to the low-resistance state has been developed. This technique is theoretically capable of holding the maximum electric current flowing through the resistance change element in the low-resistance state constant at the limited current value of a current limiting transistor by using the saturation region of the transistor, thereby preventing the variation in resistance value in the low-resistance state.
Generally, however, the current limiting transistors are arranged in a peripheral circuit region in one-to-one correspondence with rows or columns in a memory cell array region. This produces an RC delay (time lag) caused by the parasitic capacitance of an interconnection (e.g., a word line or bit line) in the memory cell array region, after the resistance value of the resistance change element has changed from the high-resistance state to the low-resistance state and before the current limiting function of the current limiting transistor becomes effective.
In reality, therefore, an electric current exceeding the limited current value of the current limiting transistor flows through the resistance change element in the low-resistance state in the period of this time lag. This makes it impossible to sufficiently achieve the newly added current limiting function. Consequently, the resistance value of the resistance change element in the low-resistance state decreases more than necessary, and varies as well.
This phenomenon becomes conspicuous when memory cells in the memory cell array region are downsized and the resistance of each memory cell increases, and when interconnections (e.g., word lines and bit lines) in the memory cell array region become long as the scale of the memory cell array increases.
On the other hand, adding one current limiting transistor to one resistance change element eliminates the above-described problem caused by the RC delay. However, this makes it necessary to sacrifice features such as a low cost obtained by the use of a simplified process, and a large capacity obtained by the use of a three-dimensional (cross-point type) memory cell array. Since the merits of a two-terminal element are thus spoiled, the use of this arrangement is unrealistic.